FIGS. 6A, 6B, 6C and 6D are diagrams schematically illustrating the general structure of a pipeline A/D converting circuit. With reference to FIG. 6A, this pipeline A/D converting circuit is an A/D converting circuit having a 1.5-bit/stage architecture. The converting circuit has cascade-connected stages 1 to 8, among which stages 1 to 7 produce identically configured 1.5-bit outputs (three values while stage 8 produces a 2-bit output (four values). The digital signals that are output from stages 1 to 8 are supplied to a digital error correction circuit (not shown). The digital error correction circuit adds the outputs from each of the stages and outputs a 10-bit digital value. As indicated in FIG. 6D, the digital error correction circuit adds the two bits of each of the stages 1 to 7 and the three bits of the stage 8 upon shifting these by one bit, thereby obtaining the 10-bit data.
As illustrated in FIG. 6B, a local A/D converter 10, which constitutes each stage of stages 1 to 7, includes a sample-and-hold circuit (SH) 101, a sub analog-to-digital converting circuit (sub A/D) 102, a sub digital-to-analog converting circuit (sub D/A) 103, a subtractor 104 and an amplifier 105 having an amplification factor of 2. The sub AD 102 converts an analog input (Vin) to 1.5 bits, the sub D/A 103 converts the digital signal from the sub A/D 102 to an analog signal, the subtractor 104 subtracts the output of the sub D/A 103 from the output voltage of the sample-and-hold circuit 101, and the amplifier 105 doubles and outputs the difference voltage that is output from the subtractor 104. Stage 8 has a 2-bit flash A/D.
As illustrated in FIG. 6C, the local A/D converter 10, which constitutes each stage of stages 1 to 7, includes capacitors Cf, Cs that sample the input signal (Vin). The digital-to-analog converting function is implemented by charging and discharging the capacitors Cf, Cs with a reference voltage. The capacitor Cf is connected as the feedback capacitor of an operational amplifier (op amp) and the capacitor Cs is connected to the reference signal to amplify the difference voltage between the sampled voltage and the reference voltage. The residue signal of difference voltage ×2 is delivered to the next stage to achieve conversion having a finer resolution. The reference voltage is selected based upon the output of a flash sub A/D (1.5-bit flash A/D) that converts the input signal (Vin) to a 1.5-bit digital signal. The operational amplifier (op amp) has an inverting input terminal (−) connected to the common node of capacitors Cf and Cs, a non-inverting input terminal (+) connected to ground, with the inverting input terminal (−) and non-inverting input terminal (+) being connected by a switch, and an output terminal connected to one end of the capacitor Cf by a switch. In the arrangement shown of FIG. 6C, the 1.5-bit flash A/D corresponds to the sub A/D in FIG. 6B, the capacitors Cf and Cs perform the function of the sample-and-hold circuit (SH) 101 in FIG. 6B and serve as sampling capacitors for sampling the input signal Vin, the capacitor Cf is feedback-connected between the output terminal and inverting input terminal of the operational amplifier, and the capacitor Cs is connected between the reference voltage terminal and the inverting input terminal of the operational amplifier (op amp). With this arrangement, the functions of the subtractor 104 and amplifier (×2) 105 in FIG. 6B as well as that of the operational amplifier (op amp) are achieved.
FIG. 7 is a diagram showing an example of the details of construction in FIG. 6C. FIG. 7 shows an example of the circuit arrangements of a local A/D of an n stage and a local A/D of an (n+1) stage. (Note that in the case of the 8-stage structure of FIGS. 6A to 6D, n is 1 to 6.) In FIG. 7, switches designated by φ1, φ2, φ3 and φ4 represent switches on/off controlled by control signals φ1, φ2, φ3 and φ4, respectively. FIG. 8 is a diagram illustrating an example of timing waveforms of the control signals φ1, φ2, φ3 and φ4 that control the operation of the switches in FIG. 7.
In a period in which the local A/D of the n stage samples the signal from the preceding (n−1) stage in capacitors Cf1 and Cs1, the (n+1) stage that is the succeeding stage is such that capacitor Cf2 is connected as the feedback capacitor of the operational amplifier (op amp) and capacitor Cs2 is connected to the reference voltage, whereby calculation and amplification of the residual are performed.
In time period 1, switches on/off controlled by φ1 and φ2, respectively are turned on and differential-format signals Vinn[n−1], Ninp[n−1] are sampled in the capacitors Cf1 and Cs1 of the local A/D of the n stage. Further, the differential signals Vinn[n−1] and Vinp[n−1] are subjected to an A/D conversion by the sub A/D (1.5-bit flash A/D).
More specifically, first terminals of capacitors Cf1 and Cs1 of a first set provided on the side of the inverting input terminal (−) of the operational amplifier (op amp) are connected in common to Vinn [n−1] via the switches turned on by φ2, second terminals of capacitors Cf1 and Cs1 of the first set are connected in common to the common-mode voltage terminal Vcm via the switch turned on by φ1, first terminals of capacitors Cf1 and Cs1 of a second set provided on the side of the non-inverting input terminal (+) of the operational amplifier (op amp) are connected in common to Vinp[n−1] via the switches turned on by φ2, and second terminals of capacitors Cf1 and Cs1 of the second set are connected in common to the common-mode voltage terminal Vcm via the switch turned on by φ1. The switches controlled by φ3 and φ4, respectively, are turned off. Further, the local A/D of the n stage has a non-inverting output terminal (+) and an inverting output terminal (−) connected to each other via a switch turned on by φ1.
In the local A/D of the (n+1) stage, capacitor Cf2 of a first set is connected as a feedback capacitor between the non-inverting output terminal (+) and the inverting input terminal (−) of the operational amplifier (op amp) via a switch turned on by φ1, and capacitor Cf2 of a second set is connected as a feedback capacitor between the inverting output terminal (−) and the non-inverting input terminal (+) of the operational amplifier (op amp) via a switch turned on by φ1. Capacitor Cs2 of the first set is connected between the reference voltage and the inverting input terminal (−) of the operational amplifier (op amp), capacitor Cs2 of the second set is connected between the reference voltage and the non-inverting input terminal (+) of the operational amplifier (op amp), and the residual between sampled voltage and reference voltage is calculated and amplified.
In the local A/D of the (n+1) stage, the reference voltages to which the first terminals of the capacitors Cs2 of the first and second sets are connected are decided by the output of the sub A/D (1.5-bit flash A/D) of the (n+1) stage. For example, when the output of the sub A/D is “00”, the first terminal of capacitor Cs2 of the first set is connected to reference voltage terminal Vrefp, and the first terminal of capacitor Cs2 of the second set is connected to reference voltage terminal Vrefn (switches φ2[00] are on). When the output of the sub A/D is “10”, the first terminal of capacitor Cs2 of the first set is connected to reference voltage terminal Vrefn, and the first terminal of capacitor Cs2 of the second set is connected to reference voltage terminal Vrefp (switches φ2[10] are on).
In time period 2, control signals φ3 and φ4 are HIGH and control signals φ1, φ2 are LOW. In the local A/D of the n stage, the capacitors Cf1 of the first and second sets are connected as feedback capacitors of the operational amplifier (op amp), the capacitors Cs1 of the first and second sets are connected to the reference voltages and the residual is calculated and amplified. In the local A/D of the succeeding (n+1) stage, the capacitors Cf2 and Cs2 of the first and second sets sample the outputs of the local A/D of the n stage, and the outputs of the local A/D of the n stage are subjected to the A/D conversion by the sub A/D (1.5-bit flash A/D) of the (n+1) stage.
More specifically, in the local A/D of the n stage in time period 2, the capacitors Cf1 of the first and second sets are connected as feedback capacitors between the non-inverting output terminal (+) and inverting input terminal (−) and between the inverting output terminal (−) and non-inverting input terminal (+), respectively, of the operational amplifier (op amp). The capacitors Cs1 of the first and second sets arc connected between the reference voltage and the inverting input terminal (−) of the operational amplifier (op amp) and between the reference voltage and non-inverting input terminal (+), respectively, of the operational amplifier (op amp).
In the local A/D of the n stage, the reference voltages to which the capacitors Cs1 of the first and second sets are connected are decided by the output of the sub A/D (1.5-bit flash A/D) of the n stage. For example, when the output of the sub A/D is “00”, the first terminals of capacitors Cs1 of the first and second sets are connected to reference voltage terminals Vrefp and Vrefn, respectively (switches φ4[00] are on). When the output of the sub A/D is “10”, the first terminals of capacitors Cs1 of the first and second sets are connected to reference voltage terminals Vrefn and Vrefp, respectively (switches φ4[10] are on). When the output of the sub A/D is “01”, the first terminal of capacitor Cs1 of the first set and the first terminal of capacitor Cs1 of the second set are connected to each other (switch φ4[01] is on).
In time period 3, control signals φ1 and φ2 are HIGH and control signals φ3 and φ4 are LOW. In the sampling time period of the output of the preceding stage in the local A/D of the n stage, the capacitors Cf2 of the first and second sets in the local A/D of the (n+1) stage are connected as feedback capacitors of the operational amplifier (op amp), capacitors Cs2 of the first and second sets are connected to the reference voltages and the residual is calculated and amplified.
In time period 4, control signals φ3 and φ4 are HIGH and control signals φ1 and φ2 are LOW. In the local A/D of the n stage, the capacitors Cf1 of the first and second sets are connected as feedback capacitors, the capacitors Cs1 of the first and second sets are connected to the reference voltages and the residual is calculated and amplified. In the local A/D of the (n+1) stage, which is the next stage, the capacitors Cf2 and Cs2 of the first and second sets sample the outputs of the local A/D of the n stage, and the outputs of the local A/D of the n stage are subjected to the A/D conversion by the sub A/D (1.5-bit flash A/D) of the (n+1) stage.
As described above, in the sampling time period during which the outputs of the preceding stage are sampled by the local A/D of the n stage, the local A/D of the (n+1) stage calculates and amplifies the residual that in the outputs of the local A/D of the n stage sampled in the preceding cycle, and the local A/D of the (n+1) stage samples the outputs of the local A/D of the n stage in the period during which the residual is calculated and amplified by the local A/D of the n stage.
In the example illustrated in FIG. 7, the local A/D of the n stage and the local A/D of the (n+1) stage have respective operational amplifiers (op amp). However, an example in which an operational amplifier (op amp) is shared between the local A/D of the n stage and the local A/D of the (n+1) stage also is known (for example, see Non-Patent Document 1).
FIG. 9 is a diagram illustrating an example of a structure in which an operational amplifier (op amp) is shared between n and (n+1) stages in the pipeline A/D converting circuit of FIG. 6. In FIG. 9, switches designated by φ1, φ2, φ3 and φ4 represent switches turned on and off by control signals φ1, φ2, φ3 and φ4, respectively. The timing waveforms of the control switches φ1 to φ4 that on/off control the respective switches in FIG. 9 are in accordance with the example depicted in FIG. 8. FIGS. 10, 11 and 12 illustrate, in an extracted manner, the connections formed in the circuit of FIG. 9 in time periods 1, 2 and 3, respectively.
In time period 1, as shown in FIG. 10, the switches controlled by the control signals φ1 and φ2 are turned on, and the switches controlled by the control signal φ3 are turned off. In the local A/D of the n stage, differential output signals from the local A/D of the (n−1) stage that are supplied to differential signal input terminals Vinn[n−1], Vinp[n−1] are sampled in the capacitors Cf1 and Cs1 of the first and second sets, respectively, and the output signals of the local A/D of the (n−1) stage are subjected to an A/D conversion by the sub A/D (1.5-bit flash A/D).
More specifically, with reference to FIG. 10, first terminals of the capacitors Cs1 and Cf1 of the first set are connected in common to the input terminal (inverted-input terminal) Vinn[n−1] via the switches turned on by φ2, and commonly connected second terminals of the capacitors Cs1 and Cf1 of the first set are connected to the common-mode voltage terminal Vcm via the switches turned on by φ1. First terminals of the capacitors Cs1 and Cf1 of the second set are connected in common to the input terminal (non-inverted-input terminal) Vinp[n−1] via the switches turned on by φ2, and commonly connected second terminals of the capacitors Cs1 and Cf1 of the second set are connected to the common-mode voltage terminal Vcm via the switches turned on by φ1.
In time period 1, the operational amplifier (op amp) is isolated from the capacitors Cs1 and Cf1 by the switches controlled by control signal φ3 and does not provide the function of an operational amplifying circuit in the local A/D of the n stage (this is the idle state).
Next, in time period 2, as shown in FIG. 11, the switches controlled by the control signals φ3 and φ4, respectively, are turned on, and the switches controlled by the control signals φ1 and φ2, respectively, are turned off. The local A/D of the n stage amplifies the difference voltage between the sampled output voltage of the preceding (n−1) stage and the reference voltage and outputs the amplified difference voltage to the (n+1) stage, which is the next stage. That is, the first terminal of the capacitor Cf1 of the first set is connected to the non-inverting output terminal (+) of the operational amplifier (op amp) via the switch turned on by φ3, and the second terminal of the capacitor Cf1 of the first set is connected is common with the second terminal of the capacitor Cs1 of the first set and, via the switch turned on by φ3, with the inverting input terminal (−) of the operational amplifier (op amp). The first terminal of the capacitor Cs1 of the first set is connected to the reference voltage terminal Vrefn (selected by the output of the sub A/D) via the switch turned on by φ4.
The first terminal of the capacitor Cf1 of the second set is connected to the inverting output terminal (−) of the operational amplifier (op amp) via the switch turned on by φ3, and the second terminal of the capacitor Cf1 of the second set is connected is common with the second terminal of the capacitor Cs1 of the second set and, via the switch turned on by φ3, with the non-inverting input terminal (+) of the operational amplifier (op amp). The first terminal of the capacitor Cs1 of the second set is connected to the reference voltage terminal Vrefp (selected by the output of the sub A/D) via the switch turned on by φ4.
During time period 2, in a manner similar to time period 1, the local A/D of the (n+1) stage samples the output voltages (differential output voltages) from the local A/D of the preceding n stage in the capacitors Cs2 and Cf2 of the first and second sets, and the outputs of the n stage are subjected to the A/D conversion by the sub A/D (1.5 bit flash A/D). Further, the switches controlled by φ1 are placed in the off state so that the capacitors Cs2 and Cf2 are isolated from the operational amplifier (op amp). In time period 2, the operational amplifier (op amp) functions as the operational amplifier of the local A/D of the n stage.
That is, the first terminals of the capacitors Cf2 and Cs2 of the first set in the local A/D of the (n+1) stage are connected in common to a node (N2) at the connection between the first terminal of the capacitor Cf1 of the second set in the local A/D of the n stage and the inverting output terminal (−) of the operational amplifier via the switches turned on by φ4. The commonly connected second terminals of the capacitors Cf2 and Cs2 of the first set are connected to the common-mode voltage terminal Vcm via the switch turned on by φ3. The first terminals of the capacitors Cf2 and Cs2 of the second set in the local A/D of the (n+1) stage are connected to a node (N1) at the connection between the first terminal of the capacitor Cf1 of the first set in the local A/D of the n stage and the non-inverting output terminal (+) of the operational amplifier (op amp) via the switches turned on by φ4. The commonly connected second terminals of the capacitors Cf2 and Cs2 of the second set are connected to the common-mode voltage terminal Vcm via the switch turned on by φ3. It should be noted that in the case of the arrangement shown in FIG. 11, the capacitors Cf2 and Cs2 of the local A/D of the (n+1) stage appear as a load to the operational amplifier (op amp).
In time period 3, as shown in FIG. 12, the switches controlled by φ1 and φ2, respectively, are turned on, the switches controlled by φ3 are turned off and the operation of the local A/D of the n stage is similar to that in time period 1. In the local A/D of the (n+1) stage, the capacitors Cf2 of the first and second sets undergo an inversion of polarity and are connected to the operational amplifier (op amp) as feedback capacitors. That is, the commonly connected second terminals of the capacitors Cf2 and Cs2 of the first set (the terminals that were connected to the common-mode voltage terminal Vcm in time period 2) are connected to the inverting input terminal (−) of the operational amplifier (op amp) via the switch turned on by φ1. The first terminal of the capacitor Cf2 of the first set [the end that was connected to the inverting output terminal (−) of the operational amplifier (op amp) in time period 2] is connected to the non-inverting output terminal (+) of the operational amplifier (op amp) via the switch turned on by φ1. The first terminal of the capacitor Cs2 of the first set [the end that was connected to the inverting output terminal (−) of the operational amplifier (op amp) in time period 2] is connected to the reference voltage terminal Vrefp via the switch turned on by φ2.
The commonly connected second terminals of the capacitors Cf2 and Cs2 of the second set (the terminals that were connected to the common-mode voltage terminal Vcm in time period 2) of the local A/D of the (n+1) stage are connected to the non-inverting input terminal (+) of the operational amplifier (op amp) via the switch turned on by φ1. The first terminal of the capacitor Cf2 of the second set [the end that was connected to the non-inverting output terminal (+) of the operational amplifier (op amp) in time period 2] is connected to the inverting output terminal (−) of the operational amplifier (op amp) via the switch turned on by φ1. The first terminal of the capacitor Cs2 of the second set [the end that was connected to the non-inverting output terminal (+) of the operational amplifier (op amp) in time period 2] is connected to the reference voltage terminal Vrefn via the switch turned on by φ2.
As a result of the A/D conversion of the outputs of the local A/D in the n stage, the connection is made to the reference voltage terminal Vrefp via the switch controlled by φ2 and the operational amplifier (op amp) calculates and amplifies the residual. In the local A/D of the n stage, Vinn[n−1] and Vinp[n−1] are sampled in the capacitors Cf1 and Cs1, respectively.
In the local A/D of the (n+1) stage, this time period is one in which the local A/D of the n stage does not require the operational amplifier (op amp). Therefore, the operational amplifier (op amp) can be made to function as the operational amplifier (op amp) in the local A/D of the (n+1) stage. Accordingly, in time period 3, the local A/D of the (n+1) stage is capable of operationally amplifying the residual between the sampled output from the n stage and the reference voltage corresponding to the output of the sub A/D using the operational amplifier (op amp) and can output the resultant signal to the (n+2) stage.
In the final time period 4, the local A/Ds of the n and (n+1) stages perform an operation similar to that in time period 2, and by repeating the operations of time periods 3 and 4 from this point onward, a pipeline-type A/D conversion proceeds.
[Non-Patent Document 1]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, NO. 12, December 2003, pp. 2031-2039, “A69-mW 10-bit 80-MSample/s Pipelined CMOS ADC”
[Non-Patent Document 2]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, NO. 3, March 1995, pp. 166-172, “A 10 b, 20 MSample/s, 35 mW Pipeline A/D Converter”